Computer Science 2500
Computer Organization

Rensselaer Polytechnic Institute
Spring 2009

Lecture 16: Pipelining and a Pipelined Data Path and Control
Date: Tuesday, March 31, 2009

Agenda

Bigger Lecture Assignment

Due at the start of class, Friday, April 3.

Please turn in a hard copy answer to the exercises below. We will discuss these during class, so no late submissions are accepted.

  1. P&H Exercise 4.2.4 and 4.2.6, p. 411 (reproduced below)
    When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance tradeoff. In the following three problems (of which you are only doing two), assume that we are starting with a datapath from Figure 4.2, where I-Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks have latencies of 400ps, 100ps, 30ps, 120ps, 200ps, 350ps, and 100ps, respectively, and costs of 1000, 30, 10, 100, 200, 2000, and 500, respectively. The remaining three problems (again, of which you are only doing two) in this exercise refer to the following processor improvement:
    a. Faster add, which reduces latency by 20ps for Add units, but adds a cost of 20 per unit.
    b. Larger registers, which add 100ps latency and add a cost of 200 per unit, but results in fewer loads and stores of register values which leads to 5% fewer instructions.
    4.2.4. What is the clock cycle time with and without each of these improvements?
    4.2.6. Compare the cost/performance ratio with and without each of these improvements.
  2. P&H Exercise 4.11.1, 4.11.2, 4.11.3, p. 419 (reproduced below)
    In this exercise, we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word:
    a. 10001100010000011000000000010000
    b. 00010000001000110000000000001100
    4.11.1. What are the outputs of the sign-extend and the jump "Shift left 2" unit (in the upper left of Figure 4.24) for each instruction word?
    4.11.2. What are the values of ALU control unit's inputs for each instruction?
    4.11.3. What is the new PC address after this instruction is executed? Highlight the path through which this value is determined.
  3. Suppose you add the bne instruction to the single-cycle implementation of the CPU described in P&H Section 4.4. Print a copy of Figure 4.17 and mark on it any elements that you need to add to the datapath or the control lines. Give the values of all the control signals for this instruction.
  4. Do the same to add the jal instruction. Use a second copy of the figure and mark it up, as well as specifying all the control signals.