Computer Science 2500
Computer Organization

Rensselaer Polytechnic Institute
Spring 2009

Lecture 19: Control Hazards and Exceptions; Memory Hierarchies and Caches
Date: Friday, April 10, 2009

Agenda

Lecture Assignment

Due at the start of class, Tuesday, April 14.

Please turn in a hard copy answer to the exercises below. We will discuss these during class, so no late submissions are accepted. Problems are reproduced here for the benefit of those working without the text. All Chapter 4 figures are available in the course shared area.

  1. P&H Exercise 4.25.1 and 4.25.3
    This exercise explores how exception handling affects pipeline design. The first three problems (you will only do the first and the third) refer to the following two instructions:
    a. Instruction 1: add $0, $1, $2, Instruction 2: bne $1, $2, Label
    b. Instruction 1: lw $2, 40($3), Instruction 2: nand $1, $2, $3
    4.25.1. Which exceptions can each of these instructions trigger? For each of these exceptions, specify the pipeline stage in which it is detected.
    4.25.3. If the second instruction is fetched right after the first, describe what happens in the pipeline when the first instruction causes the first exception you listed in 4.25.1. Show the pipeline execution diagram from the time the first instruction is fetched until the time the first instruction of the exception handler is completed.
  2. P&H Exercise 5.4, all parts
    Note: there is a mistake in the text's "Index" entry for the table in part b. The correct problem is below (11-5, not 11-15 as in the text).
    For a direct-mapped cache design with 32-bit addresses, the following bits of the address are used to access the cache.
    a. Tag: 31-10, Index: 9-4, Offset: 3-0
    b. Tag: 31-12, Index: 11-5, Offset: 4-0
    5.4.1. What is the cache line size (in words)?
    5.4.2. How many entries does the cache have?
    5.4.3. What is the ratio between total bits required for such a cache implementation over the data storage bits?
    Starting from power on, the following byte-addresses cache references are recorded.
    0    = 0000 0000 0000
4    = 0000 0000 0100
16   = 0000 0001 0000
132  = 0000 1000 0100
232  = 0000 1110 1000
160  = 0000 1010 0000
1024 = 0010 0000 0000
30   = 0000 0001 1110
140  = 0000 1000 1100
3100 = 0110 0001 1100
180  = 0000 1011 0100
2810 = 1010 1111 1010
    5.4.4. How many blocks are replaced?
    5.4.5. What is the hit ratio?
    5.4.6. List the final state of the cache, with each valid entry represented as a record of <index,tag,data>.