Computer Science 2500
Computer Organization

Rensselaer Polytechnic Institute
Spring 2009

Lecture 20: Memory Hierarchy: Caches
Date: Tuesday, April 14, 2009

Agenda

Lecture Assignment

Due at the start of class, Friday, April 17.

Please turn in a hard copy answer to the exercises below. We will discuss these during class, so no late submissions are accepted. Problems are reproduced here for the benefit of those working without the text. All Chapter 5 figures are available in the course shared area.

  1. P&H Exercise 5.6.4 and 5.6.5
    Cache block size (B) can affect both miss rate and miss latency. Assuming the following miss rate table, a 1-CPI machine with an average of 1.35 references (both instructions and data) per instruction, help find the optimal block size given the following miss rates for various block sizes:
    a. 8: 8%, 16: 3%, 32: 1.8%, 64: 1.5%, 128: 2%
    b. 8: 4%, 16: 4%, 32: 3%, 64: 1.5%, 128: 2%
    5.6.4. What is the optimal block size for a miss latency of 20 × B cycles?
    5.6.5. What is the optimal block size for a miss latency of 24 + B cycles?
  2. Since the time to access data for both hits and misses affects performance, designers often use an effective access time (EAT) to evaluate alternative cache designs. Effective access time can be defined as:
    EAT = thit + rmiss * tmiss
    for a hit time of thit, a miss rate of rmiss and a miss penalty of tmiss.
    a. Find the EAT for a processor with a 2 ns clock, tmiss = 20 clock cycles, rmiss = 0.05 misses per instruction, and a thit (cache access time, including hit detection) = 1 clock cycle. Assume that the read and write miss penalties are the same and ignore other write stalls.
    b. Suppose we can improve rmiss to 0.03 misses per reference by doubling the cache size. This causes the cache access time thit to increase to 1.2 clock cycles. Using the EAT as a metric, determine if this is a good trade-off.

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